`timescale 1ns/1ps
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// -----------------------------------------------------------------------------
// Project Name : 
// Author 		: HiDark
// File   		: ex2mem.sv
// Create 		: 2023-04-20 12:12:34
// Revise 		: 2023-04-20 12:12:34
// Abstract 	: 
// -----------------------------------------------------------------------------
`include "defines.svh"

module ex2mem(
	input	logic			clk,    // Clock
	input	logic			rst_n,  // Synchronous reset active low
	// write back register address and data
	input 	logic	[ 4:0]	rd      ,
	input 	logic	[31:0]	alu_out ,
	// control signals
	input 	logic			wb_src, 	// 0 alu or 1 mem
	input 	logic			wb_en,	 	//Register bank write enable
	input 	logic			mem_wr,  	// data mem write enable 
	input 	logic			mem_rd,  	// data mem read  enable  
	input 	logic	[ 2:0]	mem_ctrl, 	// data mem control signal	
	input	logic	[31:0]	mem_din,

	// write back register address
	output 	logic	[ 4:0]	wb_addr_ex2mem,
	output 	logic	[31:0]	alu_out_ex2mem ,
	// control signals
	output 	logic			wb_en_ex2mem ,	//Register bank write enable
	output 	logic			wb_src_ex2mem,	// 0 alu or 1 mem
	output 	logic			mem_wr_ex2mem,	// data mem write enable 
	output 	logic			mem_rd_ex2mem,  	// data mem read  enable
	output 	logic	[ 2:0]	mem_ctrl_ex2mem, 	// data mem control signal	
	output	logic	[31:0]	mem_din_ex2mem
	);


//=================================================================================
// Body
//=================================================================================

	always_ff @(posedge clk) begin 
		if(~rst_n) begin
			wb_en_ex2mem 	<=	'b0;	
			wb_src_ex2mem	<=	'b0;
			mem_wr_ex2mem	<=	'b0;
			mem_rd_ex2mem	<=	'b0;
			mem_ctrl_ex2mem	<=	'b0;
			mem_din_ex2mem	<=	'b0;	
		end else begin
			wb_en_ex2mem 	<=	wb_en;	
			wb_src_ex2mem	<=	wb_src;
			mem_wr_ex2mem	<=	mem_wr;
			mem_rd_ex2mem	<=	mem_rd;
			mem_ctrl_ex2mem	<=	mem_ctrl;
			mem_din_ex2mem	<=	mem_din;
		end
	end
	
	always_ff @(posedge clk) begin 
		if(~rst_n) 
			wb_addr_ex2mem	<=	'b0;			
		else
			wb_addr_ex2mem	<=	rd;

	end
	always_ff @(posedge clk) begin 
		if(~rst_n) 
			alu_out_ex2mem	<=	'b0; 			
		else
			alu_out_ex2mem	<=	alu_out; 		
	end

endmodule